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Leakage Inductance & Cross Conduction

This section shows how leakage inductance can cause shoot through conditions in a half bridge.


Uneven Leakage Inductance

Both of the switches in the half bridge should receive identical drive signals 180 degrees out of phase to ensure that shoot through does not occur.

When designing the SSTC drive circuit, there is the temptation to connect the rectified mains return line to the circuit ground and drive the bottom MOSFET using a gate drive IC to make life easier, with the top device driven from a GDT.

In another situation, your circuit layout might have longer wires / worse layout going to one MOSFET in the half bridge than to the other.

Either one of these situations will insert more leakage inductance into one of the drive circuits. There might also be added delay in the first example due to the propogation delay mismatch between the GDT and driver.

The voltage across an inductor cannot change instantaneously, as dictated by the equation V = L di/dt. Therefore, there will be a time delay between the MOSFET drive signals, which has the possibility to turn both FETs on at once.

The larger the leakage inductance, the larger the time delay and the larger the problem! I used this circuit to crudely simulate the effects of an imbalance in leakage inductance

And this is the result in terms of the waveforms and shoot through current using bipolar drive waveforms to the MOSFETs.


Even Leakage Inductance

As you can see, there is a distinct crossover between read and green drive waveforms that is causing the 30A peak in shoot through current shown by the blue line. Balancing the leakage inductance equally between the two FETs, as shown in the below circuit, improves the situation.

As can be seen, the shoot through current spike is reduced to about 7.5A peak.


The leakage inductance should remains as low as possible and be balanced between each FET drive circuit.